The semiconductor industry is driven with a desire to provide higher levels of integration. With higher levels of integration, silicon space and cost are reduced while performance and reliability are increased. Unfortunately, higher levels of integration lead to greater specificity. For example, application specific integrated circuits (ASICs) are highly specific devices that often serve the needs of only one customer.
Programmable logic devices, such as field programmable gate arrays (FPGAs), are versatile integrated circuit chips, which have internal circuitry logic with user selected connections that a user can configure to realize user-specific functions. While programmable logic is versatile, there are significant design challenges in size, routing, pin-out stability when mapping large complex functions onto a silicon platform containing programmable logic.
While programmable logic devices may be linked with separate dedicated devices, i.e., off chip devices, there are associated on/off chip delays, large board area, and high cost. Further, while programming a programmable logic to perform the desired function is possible, this is an expensive proposition and the resulting performance is often not acceptable.
Placing a programmable logic device on the same chip as a dedicated device is desirable as it eliminates the need for an off-chip interface with its associated delays, large board area and high cost. Nevertheless, placing a programmable logic device on the same chip as a dedicated device still requires an interface circuit between the devices. While a programmable logic device design may be used with different dedicated device designs, often the interface circuit between the devices must undergo an expensive and time consuming redesign depending on the input/output (I/O) interface demands of the dedicated device. Accordingly, an improved interface is desired.